Modern CMOS technology has enabled the integration of hundreds of components in a single silicon chip. Recent advances in three-dimensional (3D) stacking of integrated circuits (ICs) and other components using through-silicon vias (TSVs) promise even denser integration in a single package. The production process flow generally involves pre-fabrication (or “pre-silicon”) simulations, followed by post-fabrication (or “post-silicon”) debug and validation. Despite steady progress in pre-silicon verification methods and tools, first silicon—the initial run of a fabrication process for a particular design—is rarely bug-free. However, the post-silicon debug of such highly integrated systems is one of the major challenges for the feasibility of commercial systems.
Post-fabrication/post-silicon debug requires a relatively large engineering effort, accounting for a significant portion of the total time-to-market of the silicon product and this portion has been projected to grow. In order to keep pace with advances in system-level integration, including 3D stacking, traditional methodologies for bug localization need to be improved.